--- ./mig39/mig_39//user_design/rtl/mig_39.vhd	2013-01-15 15:30:15.000000000 +0100
+++ ./p/a/t/c/h/mig39/mig_39//user_design/rtl/mig_39.vhd	2013-01-15 15:27:15.860788313 +0100
@@ -65,7 +65,7 @@
 --*****************************************************************************
 library ieee;
 use ieee.std_logic_1164.all;
-entity mig_39 is
+entity mig_37 is
 generic
   (
             C3_P0_MASK_SIZE           : integer := 4;
@@ -95,8 +95,9 @@
                                        -- External memory data width.
     C3_MEM_ADDR_WIDTH       : integer := 13; 
                                        -- External memory address width.
-    C3_MEM_BANKADDR_WIDTH   : integer := 3 
+    C3_MEM_BANKADDR_WIDTH   : integer := 3; 
                                        -- External memory bank address width.
+    C3_CLKOUT5_DIVIDE       : integer := 10 
   );
    
   port
@@ -117,10 +118,14 @@
    mcb3_zio                                : inout  std_logic;
    mcb3_dram_udm                           : out std_logic;
    c3_sys_clk                              : in  std_logic;
-   c3_sys_rst_i                            : in  std_logic;
+   c3_sys_rst_n                            : in  std_logic;
    c3_calib_done                           : out std_logic;
    c3_clk0                                 : out std_logic;
    c3_rst0                                 : out std_logic;
+   clk_125                                 : out std_logic;
+   clk_100                                 : out std_logic;
+   pll_lock                                : out std_logic;
+   pll_lock0                                : out std_logic;
    mcb3_dram_dqs                           : inout  std_logic;
    mcb3_dram_dqs_n                         : inout  std_logic;
    mcb3_dram_ck                            : out std_logic;
@@ -165,9 +170,9 @@
    c3_p2_rd_overflow                       : out std_logic;
    c3_p2_rd_error                          : out std_logic
   );
-end mig_39;
+end mig_37;
 
-architecture arc of mig_39 is
+architecture arc of mig_37 is
 
  
 
@@ -179,6 +184,7 @@
       C_CLKOUT1_DIVIDE     : integer;
       C_CLKOUT2_DIVIDE     : integer;
       C_CLKOUT3_DIVIDE     : integer;
+      C_CLKOUT5_DIVIDE     : integer;
       C_CLKFBOUT_MULT      : integer;
       C_DIVCLK_DIVIDE      : integer;
       C_INCLK_PERIOD       : integer
@@ -194,11 +200,13 @@
       async_rst                              : out   std_logic;
       sysclk_2x                              : out   std_logic;
       sysclk_2x_180                          : out   std_logic;
+      mcb_drp_clk                            : out   std_logic;
       pll_ce_0                               : out   std_logic;
       pll_ce_90                              : out   std_logic;
       pll_lock                               : out   std_logic;
-      mcb_drp_clk                            : out   std_logic
-
+      pll_lock0                               : out   std_logic;
+      clk_125                                : out   std_logic;
+      clk_100                                : out   std_logic
       );
   end component;
 
@@ -362,7 +370,8 @@
    constant C3_CLKOUT1_DIVIDE       : integer := 1; 
    constant C3_CLKOUT2_DIVIDE       : integer := 16; 
    constant C3_CLKOUT3_DIVIDE       : integer := 8; 
-   constant C3_CLKFBOUT_MULT        : integer := 2; 
+--   constant C3_CLKFBOUT_MULT        : integer := 2; 
+   constant C3_CLKFBOUT_MULT        : integer := 10; 
    constant C3_DIVCLK_DIVIDE        : integer := 1; 
    constant C3_INCLK_PERIOD         : integer := ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2)); 
    constant C3_ARB_NUM_TIME_SLOTS   : integer := 12; 
@@ -460,7 +469,7 @@
 c3_sys_clk_p <= '0';
 c3_sys_clk_n <= '0';
 c3_selfrefresh_enter <= '0';
-c3_selfrefresh_enter <= '0';
+pll_lock <= c3_pll_lock;
 memc3_infrastructure_inst : memc3_infrastructure
 
 generic map
@@ -471,6 +480,7 @@
    C_CLKOUT1_DIVIDE                  => C3_CLKOUT1_DIVIDE,
    C_CLKOUT2_DIVIDE                  => C3_CLKOUT2_DIVIDE,
    C_CLKOUT3_DIVIDE                  => C3_CLKOUT3_DIVIDE,
+   C_CLKOUT5_DIVIDE                  => C3_CLKOUT5_DIVIDE,
    C_CLKFBOUT_MULT                   => C3_CLKFBOUT_MULT,
    C_DIVCLK_DIVIDE                   => C3_DIVCLK_DIVIDE,
    C_INCLK_PERIOD                    => C3_INCLK_PERIOD
@@ -480,16 +490,19 @@
    sys_clk_p                       => c3_sys_clk_p,
    sys_clk_n                       => c3_sys_clk_n,
    sys_clk                         => c3_sys_clk,
-   sys_rst_i                       => c3_sys_rst_i,
+   sys_rst_i                       => c3_sys_rst_n,
    clk0                            => c3_clk0,
    rst0                            => c3_rst0,
    async_rst                       => c3_async_rst,
    sysclk_2x                       => c3_sysclk_2x,
    sysclk_2x_180                   => c3_sysclk_2x_180,
+   mcb_drp_clk                     => c3_mcb_drp_clk,
    pll_ce_0                        => c3_pll_ce_0,
    pll_ce_90                       => c3_pll_ce_90,
    pll_lock                        => c3_pll_lock,
-   mcb_drp_clk                     => c3_mcb_drp_clk
+   pll_lock0                        => pll_lock0,
+   clk_125                         => clk_125,
+   clk_100                         => clk_100
    );
 
 
