This design is tailored to the Xilinx Kintex-7 KC705 board

http://www.xilinx.com/kc705

Note: This design requires that the GRLIB_SIMULATOR variable is
correctly set. Please refer to the documentation in doc/grlib.pdf for
additional information.

Note: The Vivado flow and parts of this design are still
experimental. Currently the design configuration should be left as-is.

Note: You must have Vivado 2017.3 in your path for the make targets to work.

The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO

Design specifics
----------------

* Synthesis should be done using Vivado 2017.3 or newer. For newer versions
  the MIG project may need to be updated.

* The DDR3 controller is implemented with Xilinx MIG 7-Seriesand 
  runs of the 200 MHz clock. The DDR3 memory runs at 400 MHz
  (DDR3-800).

* The AHB clock is generated by the MMCM module in the DDR3
  controller, and can be controlled via Vivado. When the 
  MIG DDR3 controller isn't present the AHB clock is generated
  from CLKGEN, and can be controlled via xconfig

* System reset is mapped to the EAST button
  (This is since the CPU RESET button pin is used for DDR VTP)

* DSU break is mapped to GPIO east button

* LED 0 indicates processor in debug mode

* LED 1 indicates processor in error mode, execution halted

* LED 2 indicates DDR3 PHY initialization done (Only valid when MIG is present)

* LED 3 indicates internal PLL has locked (Only valid when MIG isn't present)

* 16-bit flash prom can be read at address 0. It can be programmed
  with GRMON version 2.0.30-74 or later.

* The application UART1 is connected to the USB/RS232 connector

* The JTAG DSU interface is enabled and accesible via the JTAG port.
  Start grmon with -digilent to connect.

Simulation and synthesis
------------------------

The design uses the Xilinx MIG memory interface with an AHB-2.0
interface. The MIG source code cannot be distributed due to the
prohibitive Xilinx license, so the MIG must be re-generated with 
Vivado before simulation and synthesis can be done.

Xilinx MIG interface will automatically be generated when 
Vivado is launched  

To simulate using XSIM and run systest.c on the design using the memory 
controller from Xilinx use the make targets:

  make soft
  make vivado-launch

To simulate using Modelsim/Aldec and run systest.c on the design using 
the memory controller from Xilinx use the make targets:

  make map_xilinx_7series_lib
  make sim
  make mig_7series
  make sim-launch

To simulate using Aldec Riviera WS flow use the following make targets:

  make riviera_ws               # creates riviera workspace
  make map_xilinx_7series_lib   # compiles and maps xilinx sim libs
  make mig_7series              # generates MIG IP and adds to riviera project
  make riviera                  # compile full project
  make riviera-launch           # launch simulation

To synthesize the design, do

  make vivado

and then use the programming tool:
  
  make vivado-prog-fpga

to program the FPGA.

After successfully programmed the FPGA the user might have to press
the 'EAST' button in order to successfully complete the calibration
process in the MIG. Led 1 and led 2 should be constant green if the
Calibration process has been successful.

If user tries to connect to the board and the MIG has not been
calibrated successfully 'grmon' will output: AMBA plug&play not found!

The MIG IP can be disabled deselecting the memory controller in 'xconfig'.
When no MIG is present in the system normal GRLIB flow can be used and no extra 
compile steps are needed. Also when when no MIG is present it 
is possible to control and set the system frequency via xconfig. 
Note that the system frequency can be modified via Vivado when the MIG is present
by modifying within specified limits for the MIG IP.

Compiling and launching modelsim when no memory controller and no ethernet interface
is present using Modelsim/Aldec simulator:

  make vsim
  make soft
  make vsim-launch

Simulation options
------------------

All options are set either by editing the testbench or specify/modify the generic 
default value when launching the simulator. For Modelsim use the option "-g" i.e.
to enable processor disassembly to console launch modelsim with the option: "-gdisas=1"

USE_MIG_INTERFACE_MODEL - Use MIG simulation model for faster simulation run time
(Option can now be controlled via 'make xconfig')

disas - Enable processor disassembly to console

Selecting External FLASH
------------------------

The KC705 ref design supports Linear BPI flash and Quad SPI flash. Due
to shared pins on the FPGA the two flash types can't co-exist in the design. 
Select flash type by enabling LEON2 memory controller for BPI flash or 
SPIMCTRL for Quad SPI flash in the configuration files for the design.

Quad SPI flash memory is controlled by the configuration mode settings on DIP switch 
SW13 position 5 (M0) and a one-of-two demultiplexer device U64. If mode pin M0 = 1, the 
SPI flash memory device is selected. If mode pin M0 = 0, the Linear BPI flash memory 
device is selected.

Quad SPI flash is only supported by grmon2-2.0.56 or later

FPGA configuration
------------------

The BPI flash can be programmed by issuing the command make ise-prog-prom.

The configuration mode setting for SW13 should be M[2:0] = 010 and the full
SW13 should be:

     SW13-1     off
     SW13-2     off
     SW13-3     off
     SW13-4     on
     SW13-5     off

GRMON
------------------
To connect with grmon use

grmon -digilent

or

grmon -eth 192.168.0.170

  GRMON debug monitor v3.2.3-53-g5cec9a2 64-bit internal version
  
  Copyright (C) 2020 Cobham Gaisler - All rights reserved.
  For latest updates, go to http://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com
  
  This internal version will expire on 18/06/2021

Parsing -eth 192.168.0.170

Commands missing help:

 Ethernet startup...
WARNING! Stack pointer not set
  GRLIB build version: 4252
  Detected frequency:  100.0 MHz
  
  Component                            Vendor
  LEON5 SPARC V8 Processor             Cobham Gaisler
  GR Ethernet MAC                      Cobham Gaisler
  LEON5 Debug Support Unit             Cobham Gaisler
  AHB Debug UART                       Cobham Gaisler
  JTAG Debug Link                      Cobham Gaisler
  EDCL master interface                Cobham Gaisler
  LEON2 Memory Controller              European Space Agency
  L2-Cache Controller                  Cobham Gaisler
  AHB/APB Bridge                       Cobham Gaisler
  Gaisler RGMII Interface              Cobham Gaisler
  AMBA Wrapper for OC I2C-master       Cobham Gaisler
  Generic UART                         Cobham Gaisler
  Multi-processor Interrupt Ctrl.      Cobham Gaisler
  Modular Timer Unit                   Cobham Gaisler
  
  Use command 'info sys' to print a detailed report of attached cores

grmon3> stack 0x80000000
   CPU 0 stack pointer: 0x80000000
  
grmon3> info sys
  cpu0      Cobham Gaisler  LEON5 SPARC V8 Processor    
            AHB Master 0
  greth0    Cobham Gaisler  GR Ethernet MAC    
            AHB Master 1
            APB: 800c0000 - 80100000
            IRQ: 3
            1000 Mbit capable
            edcl ip 192.168.0.170, buffer 2 kbyte
  dsu0      Cobham Gaisler  LEON5 Debug Support Unit    
            AHB Master 2
            AHB: 90000000 - a0000000
            AHB trace: 256 lines, 64-bit bus
            CPU0:  win 8, nwp 2, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU
                   stack pointer 0x80000000lx
                   icache 4 * 4 kB, 32 B/line, rnd
                   dcache 4 * 4 kB, 32 B/line, rnd
  ahbuart0  Cobham Gaisler  AHB Debug UART    
            AHB Master 3
            APB: 80000700 - 80000800
            Baudrate 115200, AHB frequency 100.00 MHz
  ahbjtag0  Cobham Gaisler  JTAG Debug Link    
            AHB Master 4
  adev5     Cobham Gaisler  EDCL master interface    
            AHB Master 5
  mctrl0    European Space Agency  LEON2 Memory Controller    
            AHB: 00000000 - 20000000
            APB: 80000000 - 80000100
            16-bit prom @ 0x00000000
  l2cache0  Cobham Gaisler  L2-Cache Controller    
            AHB: 40000000 - 80000000
            AHB: ff000000 - ff400000
            USR: 00000110
            L2C: 1-ways, cachesize: 64 kbytes, mtrr: 0, AHB SPLIT support
  apbmst0   Cobham Gaisler  AHB/APB Bridge    
            AHB: 80000000 - 80100000
  adev9     Cobham Gaisler  Gaisler RGMII Interface    
            APB: 80001000 - 80002000
            IRQ: 11
  i2cmst0   Cobham Gaisler  AMBA Wrapper for OC I2C-master    
            APB: 80000900 - 80000a00
            IRQ: 4
  uart0     Cobham Gaisler  Generic UART    
            APB: 80000100 - 80000200
            IRQ: 2
            Baudrate 38343, FIFO debug mode available
  irqmp0    Cobham Gaisler  Multi-processor Interrupt Ctrl.    
            APB: 80000200 - 80000300
            EIRQ: 12
  gptimer0  Cobham Gaisler  Modular Timer Unit    
            APB: 80000300 - 80000400
            IRQ: 8
            16-bit scalar, 2 * 32-bit timers, divisor 100

