
LEON5 Kintex UltraScale KCU105 board Design Template
----------------------

This design template has been built in order to instantiate a Leon5 core in a
Xilinx Kintex UltraScale KCU105 board.

Information on the KCU105 at:
https://www.xilinx.com/products/boards-and-kits/kcu105.html

---------------------
Design Requirements
---------------------

The design has been tested with the following tools:

Aldec Riviera 2018.2
Vivado 2019.2

Note: The Vivado flow and parts of this design are still
experimental. Currently the design configuration should be left as-is.

Note: You must have Vivado 2019.2 in your path for the make targets to work.

The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO

------------------
Design specifics
------------------

* Synthesis should be done using Vivado 2019.2 or newer. For newer versions,
  the MIG and SGMII projects may need to be updated.

* The DDR4 controller is implemented with Xilinx MIG IP and 
  runs off the 300 MHz clock. The DDR4 memory runs at 1200 MHz.
  The calibration procedures are handled by a Microblaze
  instance into the MIG DDR4 controller, running a C source file.

* The AHB clock is generated by the MMCM module in the DDR4
  controller, and can be controlled via Vivado. When the 
  MIG DDR4 controller isn't present, the AHB clock is generated
  from CLKGEN.

* To change the AHB data width of the design, change the constant AHB-WIDTH
  in the Makefile (Default 128) and the constants CFG_AHBDW in the file
  grlib_config_leon5.vhe and CFG_AHBDW in config.vhd
  NOTE: To use AHBWIDTH = 32 it is necessary to set  also the following
  constant in config.vhd:
  +  constant CFG_BWMASK : integer := 16#0000#;


* System reset is mapped to the CPU RESET button.

* DSU break is mapped to GPIO east button (button 4). !! DISCONNECTED  FOR NOW

* LED 0-3 are connected to GPIO signals

* LED 4 indicates which UART is connected 

* LED 5 indicates processor in error mode, execution halted

* LED 6 indicates that DDR4 calibration is done

* LED 7 indicates DDR4 calibration is done, when MIG present, or PLL lock otherwise.

* The application UART1 is connected to the USB/RS232 connector if 
  switch 3, located on the DIP Switch SW2 of the board, is set to OFF.
  
* The AHB UART can be enabled by setting switch 3 to ON.
  Since the board is equipped with one USB/RS232 connector, APB UART1 and
  AHB UART cannot be used at the same time.

* The JTAG DSU interface is enabled and accessible via the JTAG port.
  Start grmon with -digilent to connect.


************************
Simulation
************************

* The design does not support DDR4 MIG simulation models and GRETH IPs (to simulate set CFG_GRETH=0). 
* An AHBRAM loaded with the ram.srec image is instantiated only if you opt for the DDR4 memory (CFG_MIG_7SERIES =1). This will instantiate and ahbramsim with the image loaded.
* An AHBROM will be also loaded during simulation.
* No ram.srec file will be loaded during simulation if you instantiate the on-chip ahbram.

By default ram.srec (and ram-be.srec) includes simple tests, compiled via the 'make soft' target.

To simulate using Aldec and run systest.c on the Leon use the make targets:

  make map_xilinx_7series_lib
  make sim
  make sim-launch

************************
Synthesize
************************

You could launch the Vivado GUI with the following target:

make vivado-launch

If you would like to run in batch mode, then issue the following commands:

make vivado

After successfully programming the FPGA the user might have to press
the 'CPU RESET' button in order to successfully complete the
calibration process in the MIG. Led 6 and led 7 should be constant
green if the Calibration process has been successful.

If user tries to connect to the board and the MIG has not been
calibrated successfully 'grmon' will output: AMBA plug&play not found!


***********************
GRMON
***********************
To connect with GRMON:

grmon -digilent

or

grmon -eth 192.168.0.51 

  GRMON debug monitor v3.2.3-53-g5cec9a2 64-bit internal version
  
  Copyright (C) 2020 Cobham Gaisler - All rights reserved.
  For latest updates, go to http://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com
  
  This internal version will expire on 18/06/2021

Parsing -digilent

Commands missing help:

JTAG chain (1): xcku040 
  Device ID:           0x288
  GRLIB build version: 4252
  Detected frequency:  100.0 MHz
  
  Component                            Vendor
  LEON5 SPARC V8 Processor             Cobham Gaisler
  GR Ethernet MAC                      Cobham Gaisler
  LEON5 Debug Support Unit             Cobham Gaisler
  AHB Debug UART                       Cobham Gaisler
  JTAG Debug Link                      Cobham Gaisler
  EDCL master interface                Cobham Gaisler
  Xilinx MIG Controller                Cobham Gaisler
  L2-Cache Controller                  Cobham Gaisler
  AHB/APB Bridge                       Cobham Gaisler
  XILINX SGMII Interface               Cobham Gaisler
  General Purpose I/O port             Cobham Gaisler
  Generic UART                         Cobham Gaisler
  Multi-processor Interrupt Ctrl.      Cobham Gaisler
  Modular Timer Unit                   Cobham Gaisler
  
  Use command 'info sys' to print a detailed report of attached cores

grmon3> info sys
  cpu0      Cobham Gaisler  LEON5 SPARC V8 Processor    
            AHB Master 0
  greth0    Cobham Gaisler  GR Ethernet MAC    
            AHB Master 1
            APB: 800c0000 - 80100000
            IRQ: 5
            1000 Mbit capable
            edcl ip 192.168.0.175, buffer 2 kbyte
  dsu0      Cobham Gaisler  LEON5 Debug Support Unit    
            AHB Master 2
            AHB: 90000000 - a0000000
            AHB trace: 256 lines, 128-bit bus
            CPU0:  win 8, nwp 2, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU
                   stack pointer 0x7ffffff0lx
                   icache 4 * 4 kB, 32 B/line, rnd
                   dcache 4 * 4 kB, 32 B/line, rnd
  ahbuart0  Cobham Gaisler  AHB Debug UART    
            AHB Master 3
            APB: 80000000 - 80000100
            Baudrate 115200, AHB frequency 100.00 MHz
  ahbjtag0  Cobham Gaisler  JTAG Debug Link    
            AHB Master 4
  adev5     Cobham Gaisler  EDCL master interface    
            AHB Master 5
  mig0      Cobham Gaisler  Xilinx MIG Controller    
            AHB: 40000000 - 80000000
            SDRAM: 1024 Mbyte
  l2cache0  Cobham Gaisler  L2-Cache Controller    
            AHB: 40000000 - 80000000
            AHB: ff000000 - ff400000
            USR: 00000110
            L2C: 4-ways, cachesize: 512 kbytes, mtrr: 0, AHB SPLIT support
  apbmst0   Cobham Gaisler  AHB/APB Bridge    
            AHB: 80000000 - 80100000
  adev9     Cobham Gaisler  XILINX SGMII Interface    
            APB: 80001000 - 80002000
            IRQ: 11
  gpio0     Cobham Gaisler  General Purpose I/O port    
            APB: 80000a00 - 80000b00
  uart0     Cobham Gaisler  Generic UART    
            APB: 80000100 - 80000200
            IRQ: 2
            Baudrate 38343, FIFO debug mode available
  irqmp0    Cobham Gaisler  Multi-processor Interrupt Ctrl.    
            APB: 80000200 - 80000300
            EIRQ: 12
  gptimer0  Cobham Gaisler  Modular Timer Unit    
            APB: 80000300 - 80000400
            IRQ: 8
            16-bit scalar, 2 * 32-bit timers, divisor 100

  
***********************
Write BPI Flash
***********************

If you would like to write bitstream into the BPI flahs in order to boot the board to that
particular design, you could issue the following command in Vivado (in a tcl shell):

* not supported yet *

And program the Quad-SPI Flash Memory using the following part name:

N25Q256A11ESF40F

The set to boot from the configuration memory in the Vivado Hardware Manager utility.

