LEON5 Virtex Ultrascale+ VCU128 board Design Template 
----------------------

This design template has been built in order to instantiate a Leon5 core in a Xilinx
Virtex Ultrascale+ VCU128 board.

Information on the VCU118 at:

https://www.xilinx.com/products/boards-and-kits/vcu128.html

---------------------
Design Requirements
---------------------

The design has been tested with the following tools:

Mentor Questasim 2021.3
Vivado 2020.2

The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO
------------------
Design specifics
------------------
* Synthesis should be done using Vivado 2020.2 or newer. For newer versions,
  the MIG and SGMII .xci files may need to be updated.

* The DDR4 controller is implemented with Xilinx MIG IP and 
  runs off the 100 MHz clock. The DDR4 memory runs at 1333 MHz.
  The calibration procedures are handled by a Microblaze
  instance into the MIG DDR4 controller, running a C source file.

* The AHB clock is generated by the MMCM module in the DDR4
  controller, and can be controlled via Vivado. When the 
  MIG DDR4 controller isn't present, the AHB clock is generated
  from CLKGEN. 
  This design has a MIG .xci which is configured to generate 100MHz clock which is used as AHB clock

* System reset is mapped to the CPU RESET button.

* DSU break is hardcoded as '1' because of the GPIO limitation on the board.

* LED 4 indicates active low system restet status.

* LED 5 indicates UART is connected 

* LED 6 indicates CPU0 error mode indication(active low)

* LED 7 indicates DDR4 calibration is done, when MIG present, or PLL lock otherwise.

* All other LEDs are tied to ground.

* The JTAG DSU interface is enabled and accessible via the USB to JTAG/UART port.
  Start grmon with -ftdi to connect.

************************
Simulate
************************

* The design does not support DDR4 MIG simulation models.
 
* An AHBROM will be also loaded during simulation.

By default ram.srec (and ram-be.srec) includes simple tests, compiled via the 'make soft' target.

To simulate using questasim and run systest.c on the Leon use the make targets:

  make map_xilinx_7series_lib
  make sim
  make sim-launch

************************
Synthesize
************************

You could launch the Vivado GUI with the following target:

make vivado-launch

If you would like to run in batch mode, then issue the following commands:

make vivado

***********************
Connecting with GRMON
***********************
If connecting to JTAG port and USB cable:
grmon -ftdi

If connecting using Xilinx Platform Cable:
grmon -xilusb

If connecting using Ethernet:

Please connect to the design using jtag debug link and issue the commands:
       source conf_eth_phy.tcl
       setup_eth sgmii_apb_addr 0
This will set up the PHY registers and establish a successful link. After that disconnect from the design and 
use the following command to connect to the design over EDCL.

grmon -eth 192.168.0.51 
(Please make sure to set up unique IP and MAC addresses for both
EDCL and greth interface to avoid any IP conflicts. Please refer to grmon3.pdf for instructions)

***********************
Output from GRMON
***********************

* FTDI
---------
grmon -u -ftdi

  GRMON debug monitor v3.3.9-24-gcd8031c 64-bit internal version
  
  Copyright (C) 2024 Frontgrade Gaisler - All rights reserved.
  For latest updates, go to https://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com
  
  This internal version will expire on 06/02/2025

Parsing -u
Parsing -ftdi

Commands missing help:
 echotrace
 package

JTAG chain (1): xcvu37p 
  Device ID:           0x288
  GRLIB build version: 4290
  Detected frequency:  100.0 MHz

  Component                            Vendor
  LEON5 SPARC V8 Processor             Frontgrade Gaisler
  GR Ethernet MAC                      Frontgrade Gaisler
  LEON5 Debug Support Unit             Frontgrade Gaisler
  AHB Debug UART                       Frontgrade Gaisler
  JTAG Debug Link                      Frontgrade Gaisler
  EDCL master interface                Frontgrade Gaisler
  AHB/APB Bridge                       Frontgrade Gaisler
  Xilinx MIG Controller                Frontgrade Gaisler
  Generic UART                         Frontgrade Gaisler
  Multi-processor Interrupt Ctrl.      Frontgrade Gaisler
  Modular Timer Unit                   Frontgrade Gaisler

  Use command 'info sys' to print a detailed report of attached cores

grmon3> info sys
  cpu0       Frontgrade Gaisler  LEON5 SPARC V8 Processor    
             AHB Master 0
  greth0     Frontgrade Gaisler  GR Ethernet MAC    
             AHB Master 1
             APB: 80040000 - 80080000
             IRQ: 5
             edcl ip 192.168.0.51, buffer 2 kbyte
  dsu0       Frontgrade Gaisler  LEON5 Debug Support Unit    
             AHB Master 2
             AHB: 90000000 - a0000000
             AHB trace: 256 lines, 128-bit bus
             CPU0:  win 8, nwp 2, itrace 256, V8 mul/div, srmmu, lddel 1, NanoFPU
                    stack pointer 0x1ffffff0
                    icache 4 * 4 kB, 32 B/line, rnd
                    dcache 4 * 4 kB, 32 B/line, rnd, snoop tags
  ahbuart0   Frontgrade Gaisler  AHB Debug UART    
             AHB Master 3
             APB: 80000000 - 80000100
             Baudrate 115200, AHB frequency 100.00 MHz
  ahbjtag0   Frontgrade Gaisler  JTAG Debug Link    
             AHB Master 4
  edcl0      Frontgrade Gaisler  EDCL master interface    
             AHB Master 5
  apbmst0    Frontgrade Gaisler  AHB/APB Bridge    
             AHB: 80000000 - 80100000
  mig0       Frontgrade Gaisler  Xilinx MIG Controller    
             AHB: 00000000 - 20000000
             SDRAM: 512 Mbyte
  uart0      Frontgrade Gaisler  Generic UART    
             APB: 80000100 - 80000200
             IRQ: 2
             Baudrate 38343, FIFO debug mode available
  irqmp0     Frontgrade Gaisler  Multi-processor Interrupt Ctrl.    
             APB: 80000200 - 80000300
             EIRQ: 12
  gptimer0   Frontgrade Gaisler  Modular Timer Unit    
             APB: 80000300 - 80000400
             IRQ: 8
             16-bit scalar, 3 * 32-bit timers, divisor 100

grmon3> edcl
  Device index: greth0
  EDCL ip 192.168.0.51
  EDCL mac 00:05:00:00:02:00
  EDCL buffer size 2 kB

grmon3> q

Exiting GRMON

* Ethernet
-----------------
grmon -u -eth 192.168.0.236

  GRMON debug monitor v3.3.9-24-gcd8031c 64-bit internal version
  
  Copyright (C) 2024 Frontgrade Gaisler - All rights reserved.
  For latest updates, go to https://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com
  
  This internal version will expire on 06/02/2025

Parsing -u
Parsing -eth 192.168.0.236

Commands missing help:
 echotrace
 package

 Ethernet startup...
  Device ID:           0x288
  GRLIB build version: 4290
  Detected frequency:  100.0 MHz

  Component                            Vendor
  LEON5 SPARC V8 Processor             Frontgrade Gaisler
  GR Ethernet MAC                      Frontgrade Gaisler
  LEON5 Debug Support Unit             Frontgrade Gaisler
  AHB Debug UART                       Frontgrade Gaisler
  JTAG Debug Link                      Frontgrade Gaisler
  EDCL master interface                Frontgrade Gaisler
  AHB/APB Bridge                       Frontgrade Gaisler
  Xilinx MIG Controller                Frontgrade Gaisler
  Generic UART                         Frontgrade Gaisler
  Multi-processor Interrupt Ctrl.      Frontgrade Gaisler
  Modular Timer Unit                   Frontgrade Gaisler

  Use command 'info sys' to print a detailed report of attached cores

grmon3> info sys
  cpu0       Frontgrade Gaisler  LEON5 SPARC V8 Processor    
             AHB Master 0
  greth0     Frontgrade Gaisler  GR Ethernet MAC    
             AHB Master 1
             APB: 80040000 - 80080000
             IRQ: 5
             edcl ip 192.168.0.236, buffer 2 kbyte
  dsu0       Frontgrade Gaisler  LEON5 Debug Support Unit    
             AHB Master 2
             AHB: 90000000 - a0000000
             AHB trace: 256 lines, 128-bit bus
             CPU0:  win 8, nwp 2, itrace 256, V8 mul/div, srmmu, lddel 1, NanoFPU
                    stack pointer 0x1ffffff0
                    icache 4 * 4 kB, 32 B/line, rnd
                    dcache 4 * 4 kB, 32 B/line, rnd, snoop tags
  ahbuart0   Frontgrade Gaisler  AHB Debug UART    
             AHB Master 3
             APB: 80000000 - 80000100
             Baudrate 115200, AHB frequency 100.00 MHz
  ahbjtag0   Frontgrade Gaisler  JTAG Debug Link    
             AHB Master 4
  edcl0      Frontgrade Gaisler  EDCL master interface    
             AHB Master 5
  apbmst0    Frontgrade Gaisler  AHB/APB Bridge    
             AHB: 80000000 - 80100000
  mig0       Frontgrade Gaisler  Xilinx MIG Controller    
             AHB: 00000000 - 20000000
             SDRAM: 512 Mbyte
  uart0      Frontgrade Gaisler  Generic UART    
             APB: 80000100 - 80000200
             IRQ: 2
             Baudrate 38343, FIFO debug mode available
  irqmp0     Frontgrade Gaisler  Multi-processor Interrupt Ctrl.    
             APB: 80000200 - 80000300
             EIRQ: 12
  gptimer0   Frontgrade Gaisler  Modular Timer Unit    
             APB: 80000300 - 80000400
             IRQ: 8
             16-bit scalar, 3 * 32-bit timers, divisor 100

grmon3> q

Exiting GRMON




