Leon3 Kintex UltraScale KCU105 board Design Template
----------------------

This design template has been built in order to instantiate a Leon3 core in a
Xilinx Kintex UltraScale KCU105 board.

Information on the KCU105 at:

https://www.xilinx.com/products/boards-and-kits/kcu105.html

---------------------
Design Requirements
---------------------

The design has been tested with the following tools:

Mentor Modelsim 10.6a
Vivado 2018.1

Note: The Vivado flow and parts of this design are still
experimental. Currently the design configuration should be left as-is.

Note: You must have Vivado 2018.1 in your path for the make targets to work.

The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO

------------------
Design specifics
------------------

* Synthesis should be done using Vivado 2018.1 or newer. For newer versions,
  the MIG and SGMII projects may need to be updated.

* This design has GRFPU enabled by default. If your release doesn't contain
  GRFPU, it has to be disabled in order to build the design.

* The DDR4 controller is implemented with Xilinx MIG IP and 
  runs off the 300 MHz clock. The DDR4 memory runs at 1200 MHz.
  The calibration procedures are handled by a Microblaze
  instance into the MIG DDR4 controller, running a C source file.

* The AHB clock is generated by the MMCM module in the DDR4
  controller, and can be controlled via Vivado. When the 
  MIG DDR4 controller isn't present, the AHB clock is generated
  from CLKGEN, and can be controlled via xconfig.

* System reset is mapped to the CPU RESET button.

* DSU break is mapped to GPIO east button (button 4)

* LED 0 indicates processor in debug mode

* LED 1 indicates processor in error mode, execution halted

* LED 5 indicates which UART is connected

* LED 6 indicates that DDR4 calibration is done

* LED 7 indicates DDR4 calibration is done, when MIG present, or PLL lock otherwise.

* 16-bit flash prom can be read at address 0. It can be programmed
  with GRMON version 2.0.30-74 or later.

* The application UART1 is connected to the USB/RS232 connector if 
  switch 3, located on the DIP Switch SW2 of the board, is set to OFF.
  
* The AHB UART can be enabled by setting switch 3 to ON.
  Since the board is equipped with one USB/RS232 connector, APB UART1 and
  AHB UART cannot be used at the same time.

* The JTAG DSU interface is enabled and accessible via the JTAG port.
  Start grmon with -digilent to connect.

----------------------
Flow
----------------------

* Simulate using local targets 

make map_xilinx_7series_lib
make sim
make ips
make sim-launch (no ram.srec if on-chip ahbram)

************************
Simulate
************************

* The design does not support DDR4 MIG.
* GRETH IP can only be simulated separately due to limitation of memory simulation model.
  To simulate the GRETH IP open systest.c and uncomment 'greth_test' and remove/comment 'base_test'
* An AHBRAM loaded with the ram.srec image is instantiated only if you opt for the DDR4 memory with 
  the CONFIG_MIG_7SERIES_MODEL variables set to Y. This will instantiate and ahbramsim with the 
   image loaded.
* No ram.srec file will be loaded during simulation if you instantiate the on-chip ahbram.

By default ram.srec (and ram-be.srec) includes simple tests, compiled via the 'make soft'
target.

Simulation options
------------------

All options are set either by editing the testbench or specify/modify the generic 
default value when launching the simulator. For Modelsim use the option "-g" i.e.
to enable processor disassembly to console launch modelsim with the option: "-gdisas=1"

USE_MIG_INTERFACE_MODEL - Use MIG simulation model for faster simulation run time
(Option can now be controlled via 'make xconfig')

disas - Enable processor disassembly to console


************************
Synthesize
************************

You could launch the Vivado GUI with the following target:

make vivado-launch

If you would like to run in batch mode, then issue the following commands:

make vivado

After successfully programming the FPGA the user might have to press
the 'CPU RESET' button in order to successfully complete the
calibration process in the MIG. Led 6 and led 7 should be constant
green if the Calibration process has been successful.

If user tries to connect to the board and the MIG has not been
calibrated successfully 'grmon' will output: AMBA plug&play not found!

************************
Flow without MIG or SGMII IPs
************************

The MIG and SGMII IP can be disabled either by deselecting the memory
controller and Gaisler Ethernet interface in 'xconfig' or manually
editing the config.vhd file.  When no MIG and no SGMII block is
present in the system normal GRLIB flow can be used and no extra
compile steps are needed. Also when when no MIG is present it is
possible to control and set the system frequency via xconfig.  Note
that the system frequency can be modified via Vivado when the MIG is
present by modifying within specified limits for the MIG IP.

Compiling and launching modelsim when no memory controller and no
ethernet interface is present using Modelsim/Aldec simulator:

  make vsim
  make soft
  make vsim-launch

***********************
Output from GRMON
***********************

Output for GRLIBConfig configuration (the output shown is for a design with MIG DDR4 controller).

# grmon -digilent


  GRMON LEON debug monitor v3.0.16-57-g39424a8 64-bit internal version

  Copyright (C) 2019 Cobham Gaisler - All rights reserved.
  For latest updates, go to http://www.gaisler.com/
  Comments or bug-reports to support@gaisler.com

  This internal version will expire on 11/12/2019

Parsing -digilent

Commands missing help:

JTAG chain (1): xcku040
  Device ID:           0xA705
  GRLIB build version: 4232
  Detected frequency:  100.0 MHz

  Component                            Vendor
  LEON3FT SPARC V8 Processor           Cobham Gaisler
  JTAG Debug Link                      Cobham Gaisler
  AHB Debug UART                       Cobham Gaisler
  AHB/APB Bridge                       Cobham Gaisler
  LEON3 Debug Support Unit             Cobham Gaisler
  Xilinx MIG DDR3 Controller           Cobham Gaisler
  Single-port AHB SRAM module          Cobham Gaisler
  Generic UART                         Cobham Gaisler
  Multi-processor Interrupt Ctrl.      Cobham Gaisler
  Modular Timer Unit                   Cobham Gaisler
  LEON3 Statistics Unit                Cobham Gaisler
  AMBA Wrapper for OC I2C-master       Cobham Gaisler
  General Purpose I/O port             Cobham Gaisler
  General Purpose I/O port             Cobham Gaisler
  Unknown device                       Cobham Gaisler

  Use command 'info sys' to print a detailed report of attached cores

grmon3> info sys
  cpu0      Cobham Gaisler  LEON3FT SPARC V8 Processor
            AHB Master 0
  ahbjtag0  Cobham Gaisler  JTAG Debug Link
            AHB Master 1
  ahbuart0  Cobham Gaisler  AHB Debug UART
            AHB Master 2
            APB: 80000700 - 80000800
            Baudrate 115200, AHB frequency 100.00 MHz
  apbmst0   Cobham Gaisler  AHB/APB Bridge
            AHB: 80000000 - 80100000
  dsu0      Cobham Gaisler  LEON3 Debug Support Unit
            AHB: D0000000 - E0000000
            AHB trace: 256 lines, 64-bit bus
            CPU0:  win 8, nwp 4, itrace 256, V8 mul/div, srmmu, lddel 1, GRFPU
                   , FT
                   stack pointer 0x4ffffff0
                   icache 4 * 4 kB, 16 B/line, lru
                   dcache 4 * 4 kB, 16 B/line, lru, snoop tags
  mig0      Cobham Gaisler  Xilinx MIG DDR3 Controller
            AHB: 40000000 - 50000000
            APB: 80000400 - 80000500
            SDRAM: 256 Mbyte
  ahbram0   Cobham Gaisler  Single-port AHB SRAM module
            AHB: A0000000 - A0100000
            32-bit SRAM: 4 kB @ 0xa0000000
  uart0     Cobham Gaisler  Generic UART
            APB: 80000100 - 80000200
            IRQ: 2
            Baudrate 38343, FIFO debug mode available
  irqmp0    Cobham Gaisler  Multi-processor Interrupt Ctrl.
            APB: 80000200 - 80000300
  gptimer0  Cobham Gaisler  Modular Timer Unit
            APB: 80000300 - 80000400
            IRQ: 8
            8-bit scalar, 2 * 32-bit timers, divisor 100
  l3stat0   Cobham Gaisler  LEON3 Statistics Unit
            APB: 80010000 - 80010400
            counters: 4, i/f index: 0
  i2cmst0   Cobham Gaisler  AMBA Wrapper for OC I2C-master
            APB: 80000900 - 80000A00
            IRQ: 10
  gpio0     Cobham Gaisler  General Purpose I/O port
            APB: 80000A00 - 80000B00
  gpio1     Cobham Gaisler  General Purpose I/O port
            APB: 80000B00 - 80000C00
  adev14    Cobham Gaisler  Unknown device
            APB: 80000D00 - 80000E00
            IRQ: 13

***********************
Execute
***********************

You could execute some benchmarks on the FPGA board by first compiling the benchmark with the
following target:

make 'benchmark_name'.srec

Then you load the generated ".srec" image into the main memory at 0x40000000 and run the
executable with the following target:

load <file.srec>
run 

* Dhrystone
-----------------------------------------------

grmon3> load ./dhrystone.exe 
  40000000 .text                    153.2kB / 153.2kB   [===============>] 100%
  400264A0 .rtemsroset                 96B              [===============>] 100%
  40027500 .data                      4.4kB /   4.4kB   [===============>] 100%
  Total size: 157.64kB (585.13kbit/s)
  Entry point 0x40000000
  Image ./dhrystone.exe loaded
  
grmon3> run
  Program exited normally.

Partial output:
Dhrystone Benchmark, Version 2.1 (Language: C)
Execution starts, 1000000 runs through Dhrystone
Microseconds for one run through Dhrystone:    5.4 
Dhrystones per Second:                      184136.8 
DMIPS:                                      104.80 

* Whetstone
-----------------------------------------------

grmon3> load ./whetstone.exe
  40000000 .text                    154.5kB / 154.5kB   [===============>] 100%
  400269E0 .rtemsroset                 96B              [===============>] 100%
  40027A40 .data                      4.4kB /   4.4kB   [===============>] 100%
  Total size: 158.95kB (582.61kbit/s)
  Entry point 0x40000000
  Image ./whetstone.exe loaded
  
grmon3> run
  Program exited normally.

Partial output:
Loops: 10000, Iterations: 1, Duration: 4.835818 sec.
C Converted Double Precision Whetstones: 206.8 MIPS

* Linpack
-----------------------------------------------

grmon3> load ./linpack.exe
  40000000 .text                    158.2kB / 158.2kB   [===============>] 100%
  400278A0 .rtemsroset                 96B              [===============>] 100%
  40028900 .data                      4.4kB /   4.4kB   [===============>] 100%
  Total size: 162.64kB (585.13kbit/s)
  Entry point 0x40000000
  Image ./linpack.exe loaded
  
grmon3> run
  Program exited normally.

Partial output:
Rolled Double Precision Linpack Benchmark - PC Version in 'C/C++'
Rolled Double  Precision        4.44 Mflops 

***********************
Write BPI Flash
***********************

If you would like to write bitstream into the BPI flahs in order to boot the board to that
particular design, you could issue the following command in Vivado (in a tcl shell):

* not supported yet *

And program the Quad-SPI Flash Memory using the following part name:

N25Q256A11ESF40F

The set to boot from the configuration memory in the Vivado Hardware Manager utility.

