axis_buffer - AXI4-Stream Buffer
================================
Overview
--------
The AXI4-S buffer provides full timing decoupling to an AXI4-Stream interface.
It can be considered a synchronous FIFO of depth 2. This buffer type is also
known as a skid buffer.

            ┌─────┐
     Ready  │     │     Ready
◄───────────┤ Buf │◄────────────────────
            │     │
            └─────┘
            ┌─────┐
            │     │
      /│ ┌─►│ Buf ├─┐ │\    ┌─────┐
Data / ├─┘  │     │ └►│ \   │     │ Data
────►│ │    └─────┘   │ ├──►│ Buf ├────►
     \ ├─────────────►│ /   │     │
      \│              │/    └─────┘
Figure: AXI-S buffer architecture

Operation
---------
There are no runtime control signals to the bridge.Please refer
the the AXI4-Stream protocol standard document from Arm (IHI0022E)
for AXI4-Stream details.

Implementation
--------------
Reset
~~~~~
The AXI4-Stream buffer resets all its registers using an active low
reset. The registers are either reset synchronously or asynchronously,
depending on the GRLIB grlib_async_reset_enable configuration constant.

Endianness
~~~~~~~~~~
The AXI4-Stream buffer is endianess agnostic, no transformations of the
input data is performed.

Configuration Options
---------------------
The AXI4-Stream buffer can be configured at elaboration time using
the generics described in this section.

wl
~~
Data word length, controls the amount of data bits in the buffers.
As the buffer only accepts tdata and no tuser, the user data has to
be aggregated into the data stream.

Signal Descriptions
-------------------
clk
~~~
AXI clock.

rst
~~~
Active low reset.

s_axis_t*
~~~~~~~~~
AXI4-Stream slave interface.
Includes the following inputs:
* data
* valid
The following output:
* ready

m_axis_t*
~~~~~~~~~
AXI4-Stream master interface.
Includes the following outputs:
* data
* valid
The following input:
* ready

Library Dependencies
--------------------
GRLIB
~~~~~
config: Reset configuration definition.
config_types: Configuration support.

Instantiation
-------------
The following code snippet is intended to show how the core is instantiated.

library ieee;
use ieee.std_logic_1164.all;

library gaisler;
use gaisler.axi.all; -- AXI4-Stream component

entity axis_buffer_example is
  port (
    clk : in std_logic;
    rstn : in std_logic
  );
end entity;

architecture ex of axis_buffer_example is
  constant data_width : natural := 32;

  signal s_axis_tdata : std_logic_vector(data_width - 1 downto 0);
  signal s_axis_tvalid : std_logic := '0';
  signal s_axis_tready : std_logic;

  signal m_axis_tdata : std_logic_vector(data_width - 1 downto 0);
  signal m_axis_tvalid : std_logic;
  signal m_axis_tready : std_logic := '1';
begin
  -- Rest of the design goes here.

  skid_buffer : axis_buffer
    generic map (
      wl => data_width
    )
    port map (
      clk => clk,
      rst => rstn,

      s_axis_tdata => s_axis_tdata,
      s_axis_tvalid => s_axis_tvalid,
      s_axis_tready => s_axis_tready,

      m_axis_tdata => m_axis_tdata,
      m_axis_tvalid => m_axis_tvalid,
      m_axis_tready => m_axis_tready
    );
end architecture;
